In recent years, markets of displays are rapidly expanding as personal computers and home television receivers are becoming larger in size. At present, in the field of displays, cathode-ray tubes are most popular displays because they are excellent in visibility, such as high-definition, high-intensity, a wide angle of view and high contrast. On the other hand, as displays are becoming larger in size, such larger displays need larger areas and this increase of area receives a remarkable attention. Therefore, in addition to liquid-crystal displays and projector displays, flat panel displays such as organic electroluminescence displays that can decrease their thickness much more have been so far expected as next-generation displays instead of the cathode-ray tubes. In accordance therewith, also in the fields of semiconductors, a demand for a high withstand voltage process that can form high withstand voltage driving ICs, e.g. high withstand voltage display driver ICs is increasing.
AMOS transistor having a conventional structure, for example, has a so-called symmetrical arrangement in which second-conductivity type source region and drain region are formed on a first-conductivity type semiconductor well region serving as a back-gate region and a gate electrode is formed on the surface of the semiconductor well region between the source region and the drain region through a gate insulating film, although not shown. In such MOS transistor, as the gate length decreases, a resistance component in the channel region decreases so that the MOS transistor can operate at higher speeds. In the MOS transistor having the above-mentioned structure, however, if the gate length decreases in order to increase operation speed, then when a drain voltage increases, a depletion layer from the drain region reaches the source region to cause a breakdown and hence a withstand voltage cannot be obtained.
Accordingly, as the high withstand voltage MOS transistor, there has been so far developed an offset drain type lateral operation MOS transistor in which a source-drain withstand voltage can increase, i.e. a transistor called an LD (lateral diffused) MOS transistor. FIG. 8 shows an example of an offset drain type high withstand voltage MOS transistor. This example is applied to an n-channel MOS transistor. This high withstand voltage MOS transistor 18 has a structure in which an offset drain region 20 formed of a lightly-doped n− semiconductor region is fabricated into a p-type semiconductor well region 6 that serves as a back-gate electrode. Specifically, after an n-type epitaxial layer 5 had been epitaxially deposited on a first-conductivity type, e.g. p-type silicon semiconductor substrate 2 through a second-conductivity type n-type buried layer 4, an element separation region e.g. element forming region separated by a field insulating layer 3 formed by selective oxidation (so-called LOCOS) is formed. A p-type semiconductor well region 6 is formed within this element forming region to oppose the surface such that it may contact with the n-type buried layer 4. An n semiconductor region having an impurity concentration lower than that of a drain region 8D, e.g. so-called off-set drain region 20 is formed within this p-type semiconductor well region 6. Then, a heavily-doped n+ source region 8S is formed within the p-type semiconductor well region 6 and a heavily-doped n+ drain region 8D is formed distant from the gate within the offset drain region 20. A gate electrode 10 is formed on the surface of a channel region 8C formed of the p-type semiconductor well region 6 between the source region 8S and the off set drain region 20 through an insulating gate film 9. A source electrode 11S and a drain electrode 11D are interconnected to the source electrode 8S and the drain electrode 8D, respectively. Reference numeral 12 denotes an insulating film made of a suitable material such as SiO2. The high withstand voltage MOS transistor is constructed in this manner. In the offset drain type high withstand voltage MOS transistor 18, an electric field can be relaxed and a withstand voltage can be increased by expanding a depletion layer generated by applying a drain voltage to the side of the offset drain region 20 formed of the lightly-doped n− semiconductor region. In the high withstand voltage MOS transistor 18 shown in FIG. 8, another process for forming the offset drain region 20 should be added.
On the other hand, there has been proposed an offset drain type high withstand voltage MOS transistor having a structure that can be manufactured with the existing processes without addition of processes when the offset drain type high withstand voltage MOS transistor is applied to a CMOS transistor. FIG. 7A shows a fundamental structure of an offset drain type high withstand voltage MOS transistor that can be manufactured with the existing processes of the CMOS transistor.
This high withstand voltage MOS transistor 1 is formed within an element separation region, e.g. an element forming region separated by a field insulating layer 3 formed by selective oxidation (so-called LOCOS) after an n-type epitaxial layer 5 had been epitaxially deposited on a first-conductivity type, e.g. p-type silicon semiconductor substrate 2 through a second-conductivity type, e.g. n-type buried layer 4. Specifically, a p-type semiconductor well region 6 serving as a back-gate region and an n− semiconductor region having a concentration lower than an impurity concentration of the drain region, i.e. so-called offset drain region 7 are formed within this element forming region to oppose the surface such that they may contact with the n-type buried layer 4. A p-type element forming layer beneath the field insulating layer 3, i.e. so-called channel stopper layer 19 is formed with the same process at the same time the p-type well region 6 is formed. A heavily-doped n+ source region 8S is formed within the p-type semiconductor well region 6 and a heavily-doped n+ drain region 8D is formed distant from the gate within the n− semiconductor region 7 that is the offset drain region. Then, a gate electrode 10 is formed on a surface extending from a channel 8c formed of the P-type semiconductor well region to a part of the n− semiconductor region 7 that is the offset drain region. A source electrode 11S and a drain electrode 11D are respectively interconnected to the source region 8S and the drain region 8D. Reference numeral 12 denotes an insulating film made of a suitable material such as SiO2. The high withstand voltage MOS transistor 1 is constructed in this manner.
In this high withstand voltage MOS transistor 1, similarly as described above, when a reverse bias is applied between the source electrode 11S and the drain electrode 11D, the depletion layer expands from a pn junction between the p-type semiconductor well region 6 and the offset drain region (also referred to as a “drift region”) formed of the n− semiconductor region to the n− semiconductor region 7. The electric field is relaxed by using the expansion of the depletion layer toward the n semiconductor region 7, whereby the withstand voltage of the MOS transistor can be maintained.
When the above-mentioned high withstand voltage MOS transistor 1 is applied to the CMOS transistor, the above-described offset drain region 7 comprising one second-conductivity type channel MOS transistor is formed at the same time a semiconductor well region serving as a back-gate region in the other first-conductivity type channel MOS transistor formed in other region, not shown, is formed. Specifically, when the high withstand voltage MOS transistor 1 is formed as one n-channel MOS transistor comprising the CMOS transistor, the offset drain region 7 formed of the lightly-doped n semiconductor region interconnected to the n+ drain region 8D is formed at the same time in the process in which the n-type semiconductor well region serving as the back-gate of the other p-channel MOS transistor comprising the CMOS transistor is formed. Consequently, it is possible to manufacture the CMOS transistor including the offset drain type high withstand voltage MOS transistor with the number of the existing processes.
In the above-mentioned high withstand voltage MOS transistor 1, since one process serves both as the process for forming the element separation layer (p-type channel stopper layer) 19 and the process for forming the p-type semiconductor well region 6, after the n-type epitaxial layer 5 had been epitaxially deposited and the field insulating layer 3 had been formed as shown in FIG. 7B, the element separation layer 19 and the p-type semiconductor well region 6 are formed at the same time. Specifically, after the field insulating layer 3 had been formed, a photoresist mask 14 having an opening 14a across a part of the field insulating layer 3 and an opening 14b located on the field insulating layer 3 is formed by patterning a positive type photoresist film, for example, and the p-type semiconductor well region 6 and the element separation layer (p-type channel stopper layer) 19 are formed by implanting ions of p-type impurities, e.g. ions of boron 15 through this photoresist mask 14. Having considered the case in which the element separation layer 19 is formed, ion implantation conditions are designed in such a manner that the impurity concentration may reach a peak 15 on the surface (accordingly, the depth position) of the n-type epitaxial layer 5 beneath the field insulating layer 3. In the positive type photoresist mask 14, the end portions of the opening portions 14a, 14b are formed like tapered end portions as illustrated in order to prevent interference of light required when the photoresist film is exposed thereto.
In the above-mentioned high withstand voltage MOS transistor 1, the field insulating layer 3 has a film thickness of approximately 800 nm, for example, and energy for implanting ions is approximately 360 keV. The film thickness of the photoresist mask 14 should increase as energy for implanting ions increases as described above, and the photoresist mask needs a film thickness of about 2.4 μm. One process can serve both as one process and the other process by optimizing the process conditions as described above.
However, there arises a serious problem that the threshold voltage Vth becomes larger than a designed value and is fluctuated as energy for implanting ions increases. Specifically, when energy for implanting ions is large as shown in FIG. 7B, the impurity ions 16 are caused to go through the photoresist mask 14 at the opening end portions (tapered end portions) of the photoresist mask 14 in the element forming region side so that the impurity concentration peak 15 moves near the surface of the n-type epitaxial layer 5 along the angle of the tapered opening end portion of the photoresist mask 14, thereby resulting in a heavily-doped impurity region 17 (see FIG. 7A) that exerts a serious influence upon the threshold voltage Vth.